Is AEC-Q100 a certification?

No. AEC-Q100 Rev J1, section 1.3.2, states that there are no "certifications" for AEC-Q100 qualification and no certification board run by the AEC to qualify parts. Each supplier runs the qualification itself, takes customer requirements into account and submits the data to the user, who verifies compliance. AEC-Q101 contains the same statement. A part described as "AEC-Q100 certified" is therefore a part whose supplier claims AEC-Q100 qualification; the evidence is the supplier's qualification report, not a certificate.

What temperature grades does AEC-Q100 define?

Four, by ambient operating temperature: Grade 0 from -40 to +150 °C, Grade 1 from -40 to +125 °C, Grade 2 from -40 to +105 °C and Grade 3 from -40 to +85 °C (Table 1 of Rev J1). The grade changes the stress conditions, not only the label: HTOL runs 1,000 hours at +150 °C ambient for Grade 0 and at +85 °C for Grade 3, and temperature cycling runs 1,500 cycles from -55 to +150 °C for Grade 0 against 500 cycles from -55 to +125 °C for Grade 3.

What are the AEC-Q100 test groups?

Seven groups in Table 2 of Rev J1. A, accelerated environment stress (preconditioning, THB or HAST, autoclave or unbiased HAST, temperature cycling, power temperature cycling, high temperature storage). B, accelerated lifetime simulation (HTOL, early life failure rate, NVM endurance and retention). C, package assembly integrity (wire bond shear and pull, solderability, dimensions, solder ball and bump shear, lead integrity). D, die fabrication reliability (EM, TDDB, HCI, BTI, stress migration). E, electrical verification (ESD HBM and CDM, latch-up, distributions, characterisation, EMC, short circuit, soft error rate). F, defect screening (part average testing, statistical bin analysis). G, cavity package integrity (shock, vibration, leak, drop, lid torque, die shear, internal water vapour).

How many parts does AEC-Q100 qualification require?

For the core stress tests (preconditioning, THB or HAST, autoclave or unbiased HAST, temperature cycling and HTOL), Table 2 of Rev J1 requires 77 parts from each of 3 lots, with zero failures. Power temperature cycling and high temperature storage life use 45 parts from one lot, also with zero failures. Generic data from a part in the same qualification family can substitute for some tests, and Rev J1 sets no time limit on the acceptability of generic data.

What is the difference between AEC-Q100, Q101, Q200 and Q006?

AEC-Q100 covers integrated circuits, AEC-Q101 discrete semiconductors and AEC-Q200 passive components. AEC-Q006, sometimes mistaken for something newer, is the qualification requirement for components using copper (Cu) wire interconnections; Rev B is dated 30 June 2025, and both Q100 and Q101 send Cu wire parts to it. Q102 covers discrete optoelectronics, the Q103 sub-documents cover MEMS pressure sensors and MEMS microphones, and Q104 covers multichip modules.

Does AEC-Q200 have temperature grades 0 to 4?

Not in the current revision. AEC-Q200 Rev E, dated 20 March 2023, sets a minimum ambient range of -40 °C to +85 °C in section 1.5.3 and asks the manufacturer to qualify each component to its own specified ambient range, using the component tables. Lists of Q200 grades 0 to 4 that circulate online describe earlier revisions. AEC-Q101 Rev E likewise has no grade table: its minimum operational range is -40 °C to +125 °C.

What ESD levels does AEC-Q100 require?

The Rev J1 targets are 2 kV HBM (classification 2 or better) and, for CDM, test condition 750 on corner pins and 500 on all other pins (classification C2A or better). For devices at 28 nm and below, or pins operating at RF frequencies, the targets are 1 kV HBM and CDM test condition 250. A level below target needs specific user approval, and an HBM target below 2 kV must be stated in the datasheet.

Does AEC-Q qualification cover functional safety?

No. AEC-Q documents qualify the physical reliability of a component under accelerated stress. Functional safety is the subject of ISO 26262, which asks for different evidence, such as failure mode analysis and diagnostic coverage. A component destined for a safety function needs both, and neither document stands in for the other.

AEC-Q100, Q101, Q200: grades, tests and sample sizes

Hugues Orgitello updated 6 Oct 2026 11 min read

AEC-Q100 is the qualification document for integrated circuits in vehicles, AEC-Q101 for discrete semiconductors and AEC-Q200 for passive components. All three are free to download from the Automotive Electronics Council, and most of what circulates about them is easier to check than to repeat. This guide is written from the documents themselves: AEC-Q100 Rev J1 of 24 March 2026, AEC-Q101 Rev E of 1 March 2021 and AEC-Q200 Rev E of 20 March 2023. It gives the grades, the seven test groups, the sample sizes, the ESD targets, and five claims about AEC-Q that the documents contradict.

In short:

AEC-Q100 has four grades, from Grade 0 (-40 to +150 °C) to Grade 3 (-40 to +85 °C), and the grade changes the stress conditions: 1,500 temperature cycles for Grade 0, 500 for Grade 3.
The core stress tests take 77 parts from each of 3 lots, with zero failures.
There is no AEC certification. The supplier qualifies the part and hands the data to the customer, as section 1.3.2 of Q100 says in so many words.
AEC-Q101 and AEC-Q200 have no grade numbers in their current revisions, only minimum temperature ranges.
AEC-Q006 is about copper wire, not a new category of component.

The AEC documents at a glance

The Council publishes a base document per component family, plus test-method sub-documents (Q100-002 for HBM, Q100-011 for CDM, Q100-004 for latch-up, and so on) and cross-family guidelines.

Document	Covers	Current revision	Temperature requirement
AEC-Q100	Integrated circuits	Rev J1, 24 March 2026	Grades 0 to 3 (Table 1)
AEC-Q101	Discrete semiconductors	Rev E, 1 March 2021	Minimum -40 to +125 °C operational
AEC-Q102	Discrete optoelectronic semiconductors	Rev A	Per document
AEC-Q103-002 / -003	MEMS pressure sensors / MEMS microphones	Rev A / initial release	Per document
AEC-Q104	Multichip modules (MCM)	Rev A, 28 November 2025	Per document
AEC-Q200	Passive components	Rev E, 20 March 2023	Minimum -40 to +85 °C, qualified to the supplier's specified range
AEC-Q006	Components using copper (Cu) wire interconnections	Rev B, 30 June 2025	Applies on top of Q100 or Q101
AEC-Q007	Components mounted to a printed board	Initial release, 12 March 2024	Testing guidelines

The cross-family guidelines complete the set: Q001 part average testing, Q002 statistical yield analysis, Q003 electrical characterisation, Q004 the zero defects framework, and Q005 lead-free requirements. Q100 lists them among its automotive references, alongside IATF 16949 and the AIAG Production Part Approval Process.

Five claims the documents contradict

1. "AEC-Q100 certified." Section 1.3.2 of Q100 Rev J1 is explicit: there are no certifications for AEC-Q100 qualification and no certification board run by the AEC. The supplier qualifies, the customer verifies. AEC-Q101 carries the same wording. The evidence to ask for is the qualification report and the test plan, not a certificate.

2. "AEC-Q200 Grade 0 to Grade 4." The current Q200, Rev E, has no grade table. Section 1.5.3 sets a minimum ambient range of -40 to +85 °C and requires the manufacturer to qualify to its own specified range. A Q200 part qualified to -55 to +150 °C says so in its datasheet and report; a grade number does not.

3. "AEC-Q101 Grades 0 to 3." Q101 Rev E also has no grade table. It sets a minimum operational ambient range of -40 to +125 °C for discrete semiconductors.

4. "AEC-Q006 is for AI chips." Q006 is titled Qualification Requirements for Components using Copper (Cu) Wire Interconnections. Q100 Rev J added a section sending Cu wire devices to it, and Q101 states that Q006 requirements supersede its own for Cu wire parts.

5. "AEC-Q requires six to twelve months' notice of a change." Q100 section 3.2.1 says only that the supplier will meet the user requirements for product and process changes. The notice period comes from the customer contract, not from the AEC document. What Q100 does define is which changes require requalification, through Appendix 1 and the test-selection guide in Table 3.

AEC-Q100 temperature grades, and what each one costs in testing

Table 1 of Q100 Rev J1 defines four grades by ambient operating temperature. The grade is not a label added at the end: Table 2 sets different stress conditions for each.

Grade	Ambient range	HTOL (B1), 1,000 hours at	Temperature cycling (A4)	High temperature storage (A6), plastic packages
0	-40 to +150 °C	+150 °C ambient	-55 to +150 °C, 1,500 cycles	+175 °C for 1,000 h, or +150 °C for 2,000 h
1	-40 to +125 °C	+125 °C ambient	-55 to +150 °C, 1,000 cycles	+150 °C for 1,000 h, or +175 °C for 500 h
2	-40 to +105 °C	+105 °C ambient	-55 to +125 °C, 1,000 cycles	+125 °C for 1,000 h, or +150 °C for 500 h
3	-40 to +85 °C	+85 °C ambient	-55 to +125 °C, 500 cycles	+125 °C for 1,000 h, or +150 °C for 500 h

For Grade 1, Q100 also accepts -65 to +150 °C for 500 cycles as a legacy condition with no known lifetime issues. For the lifetime tests of Group B, the junction temperature during stress should be at or above the hot temperature of the grade.

Two consequences for component selection follow. A Grade 3 part is not a cheaper Grade 1 part: it has seen a third of the temperature cycles over a narrower range. And the grade has to follow the mission profile of the electronic control unit, not the other way round. Rev J added section 2.3 and Appendix 7 for exactly this case: when a customer's mission profile goes beyond the standard conditions, the appendix gives a flow to decide between the standard test plan and a modified one, based on the knowledge-based test methodology of JEDEC JESD94.

The seven test groups of AEC-Q100

Table 2 of Q100 Rev J1 organises qualification into seven groups. The codes (A1, B1 and so on) are the ones used in qualification reports.

Group	Name in Rev J1	Tests
A	Accelerated environment stress	A1 preconditioning (PC), A2 temperature humidity bias or biased HAST, A3 autoclave, unbiased HAST or temperature humidity, A4 temperature cycling, A5 power temperature cycling, A6 high temperature storage life
B	Accelerated lifetime simulation	B1 high temperature operating life (HTOL), B2 early life failure rate (ELFR), B3 NVM endurance, data retention and operational life (EDR)
C	Package assembly integrity	C1 wire bond shear, C2 wire bond pull, C3 solderability, C4 physical dimensions, C5 solder ball shear, C6 lead integrity, C7 bump shear (new in Rev J)
D	Die fabrication reliability	D1 electromigration, D2 time dependent dielectric breakdown, D3 hot carrier injection, D4 bias temperature instability, D5 stress migration
E	Electrical verification	E1 pre and post stress test, E2 ESD HBM, E3 ESD CDM, E4 latch-up, E5 electrical distributions, E6 fault grading, E7 characterisation, E9 EMC, E10 short circuit characterisation, E11 soft error rate, E12 lead-free
F	Defect screening	F1 part average testing (AEC-Q001), F2 statistical bin analysis (AEC-Q002)
G	Cavity package integrity	G1 mechanical shock, G2 variable frequency vibration, G3 constant acceleration, G4 gross and fine leak, G5 package drop, G6 lid torque, G7 die shear, G8 internal water vapour

Group D tests have no sample size in the table: the supplier provides the data, method and criteria from the wafer technology qualification. Group G applies only to cavity packages, and Group F describes production screening rather than one-off stress tests.

Sample sizes and pass criteria

The headline numbers are in Table 2:

Test	Sample size per lot	Lots	Accept criterion
A1 preconditioning, A2 THB or HAST, A3 autoclave or UHST, A4 temperature cycling, B1 HTOL	77	3	0 failures
A5 power temperature cycling, A6 high temperature storage life	45	1	0 failures
G4 gross and fine leak	15	1	0 failures
G6 lid torque, G8 internal water vapour	5	1	0 failures

The humid stresses come with fixed conditions: THB at 85 °C and 85 % relative humidity for 1,000 hours, or HAST at 130 °C and 85 % for 96 hours, or 110 °C and 85 % for 264 hours. Autoclave is 121 °C at 15 psig for 96 hours, and Rev J states that unbiased HAST is strongly preferable to autoclave. Power temperature cycling is only required where the application sees repetitive power changes of 1 watt or more with rise times under 0.1 second, giving junction swings of 40 °C or more, such as smart power switches driving inductive loads.

Any failure has to be analysed for root cause, and section 3.3 makes qualification conditional on corrective and preventive actions proven effective, using the 8D method.

ESD targets

ESD robustness is tested in Group E, with separate, lower targets that Rev J added for advanced nodes and RF pins:

Model	Target	For ≤ 28 nm or RF operating pins	Test method
Human body model (E2)	2 kV, classification 2 or better	1 kV, classification 1C or better	AEC-Q100-002
Charged device model (E3)	Test condition 750 on corner pins, 500 on all others, classification C2A or better	Test condition 250, classification C1 or better	AEC-Q100-011

A level below target needs specific user approval, and an HBM target below 2 kV must be stated in the datasheet. Section 1.3.1 recommends that the passing HBM voltage and CDM condition appear in the datasheet anyway, with a footnote on pin exceptions. These component-level tests are distinct from the system-level gun test of IEC 61000-4-2, which our ESD test guide covers.

What changed in Rev J and Rev J1

Rev J, dated 11 August 2023, was the first full revision since Rev H of 11 September 2014. Its revision summary lists, among other changes:

A new section 3.6 on devices using copper wire, pointing to AEC-Q006.
A new definition and tests for flip-chip ball grid array packages, including the new C7 bump shear test.
A new section 2.3 on customer mission profiles, linked to Appendix 7.
Acoustic microscopy delamination checks after preconditioning and temperature cycling, on 3 devices from each of 3 lots.
New ESD acceptance criteria for advanced CMOS nodes.
A complete revision of Appendix 1, the definition of a qualification family.

Rev J1, dated 24 March 2026, is a narrow update: Appendix 2 is renamed Q100 Certificate of Design, Construction and its template is replaced by an Excel file.

AEC-Q101 and AEC-Q200

AEC-Q101 follows the same failure-mechanism logic for discrete semiconductors such as diodes, transistors, MOSFETs and IGBTs. Its minimum operational range is -40 to +125 °C, it uses the same 77 parts by 3 lots minimum where generic data stand in for a test, and parts with copper wire follow AEC-Q006, whose requirements supersede Q101's own. Its sub-documents cover HBM and CDM ESD, wire bond shear, miscellaneous test methods and short circuit characterisation of smart power devices for 12 V systems.

AEC-Q200 is organised differently: rather than one test table, it has one stress table per component family, sixteen in Rev E, each with its own stresses, pass criteria and process-change guide:

Table	Family	Table	Family
1	Tantalum (MnO2 and polymer) and niobium capacitors	9	Trimmer capacitors and resistors
2	Ceramic capacitors	10	Varistors
3	Aluminium electrolytic capacitors (hybrid, polymer, standard)	11	Quartz crystals
4	Film capacitors	12	Ceramic resonators
5	Magnetics (inductors, transformers)	13	Ferrite EMI suppressors and filters
6	Networks (R-C, C, R)	14	Polymeric resettable fuses
7	Resistors	15	Fuses
8	Thermistors (NTC, platinum, ceramic PTC)	16	Super capacitors

Its sub-documents cover flame retardance, HBM ESD, beam load, resettable fuse measurement, board flex and terminal bond strength, terminal shear and voltage surge. The minimum ambient range is -40 to +85 °C, and the manufacturer qualifies to its own specified range.

In a single control unit, the three documents usually coexist: the microcontroller under Q100, the power MOSFETs under Q101, the decoupling capacitors under Q200, and an optocoupler under Q102.

Where AEC-Q sits next to ISO 26262 and IATF 16949

AEC-Q is a component qualification. It shows that a part survives accelerated stress representative of its use. It does not show that a system detects and controls dangerous failures, which is the subject of ISO 26262, and it does not describe the supplier's quality system, which is the subject of IATF 16949.

The link between them runs through the customer. Q100 lists IATF 16949 and the AIAG Production Part Approval Process among its references, and in practice automotive customers ask for the AEC-Q qualification report as part of the part approval package. A component used in a safety function needs both kinds of evidence: the AEC-Q report for reliability, and the safety analysis that ISO 26262 asks of a hardware element.

A short history

The idea came out of a JEDEC meeting in the summer of 1992, between Gerald Servais of Delco Electronics, then part of General Motors, and Jerry Jennings of Chrysler, according to the Council's own history. A meeting at Delco Electronics in January 1993 compared the companies' qualification approaches, and the first release of Q100, then called CDF-AEC-Q100, was presented to IC suppliers in Denver in June 1994. It was the preferred qualification document for Chrysler, Delco Electronics and Ford, and a part qualified to it was qualified for all three. AEC-Q101 for discretes and AEC-Q200 for passives followed.

Checklist for selecting an AEC-Q part

Ask for the qualification report, not a certificate, and check the revision it was run against.
Check the grade for Q100 parts, and the stated temperature range for Q101 and Q200 parts, against the mission profile of the enclosure.
Check the exact part number in the report: qualification covers specific parts or a defined qualification family, not a whole catalogue series.
Read the ESD levels in the datasheet, especially below 28 nm or on RF pins, where Rev J accepts lower targets.
Ask whether the part uses copper wire, and if so for the AEC-Q006 data.
Agree the change notification terms in the contract, since Q100 leaves them to the user requirements.
Plan the functional safety evidence separately if the part sits in a safety function.

Frequently asked questions

Is AEC-Q100 a certification?: No. AEC-Q100 Rev J1, section 1.3.2, states that there are no "certifications" for AEC-Q100 qualification and no certification board run by the AEC to qualify parts. Each supplier runs the qualification itself, takes customer requirements into account and submits the data to the user, who verifies compliance. AEC-Q101 contains the same statement. A part described as "AEC-Q100 certified" is therefore a part whose supplier claims AEC-Q100 qualification; the evidence is the supplier's qualification report, not a certificate.
What temperature grades does AEC-Q100 define?: Four, by ambient operating temperature: Grade 0 from -40 to +150 °C, Grade 1 from -40 to +125 °C, Grade 2 from -40 to +105 °C and Grade 3 from -40 to +85 °C (Table 1 of Rev J1). The grade changes the stress conditions, not only the label: HTOL runs 1,000 hours at +150 °C ambient for Grade 0 and at +85 °C for Grade 3, and temperature cycling runs 1,500 cycles from -55 to +150 °C for Grade 0 against 500 cycles from -55 to +125 °C for Grade 3.
What are the AEC-Q100 test groups?: Seven groups in Table 2 of Rev J1. A, accelerated environment stress (preconditioning, THB or HAST, autoclave or unbiased HAST, temperature cycling, power temperature cycling, high temperature storage). B, accelerated lifetime simulation (HTOL, early life failure rate, NVM endurance and retention). C, package assembly integrity (wire bond shear and pull, solderability, dimensions, solder ball and bump shear, lead integrity). D, die fabrication reliability (EM, TDDB, HCI, BTI, stress migration). E, electrical verification (ESD HBM and CDM, latch-up, distributions, characterisation, EMC, short circuit, soft error rate). F, defect screening (part average testing, statistical bin analysis). G, cavity package integrity (shock, vibration, leak, drop, lid torque, die shear, internal water vapour).
How many parts does AEC-Q100 qualification require?: For the core stress tests (preconditioning, THB or HAST, autoclave or unbiased HAST, temperature cycling and HTOL), Table 2 of Rev J1 requires 77 parts from each of 3 lots, with zero failures. Power temperature cycling and high temperature storage life use 45 parts from one lot, also with zero failures. Generic data from a part in the same qualification family can substitute for some tests, and Rev J1 sets no time limit on the acceptability of generic data.
What is the difference between AEC-Q100, Q101, Q200 and Q006?: AEC-Q100 covers integrated circuits, AEC-Q101 discrete semiconductors and AEC-Q200 passive components. AEC-Q006, sometimes mistaken for something newer, is the qualification requirement for components using copper (Cu) wire interconnections; Rev B is dated 30 June 2025, and both Q100 and Q101 send Cu wire parts to it. Q102 covers discrete optoelectronics, the Q103 sub-documents cover MEMS pressure sensors and MEMS microphones, and Q104 covers multichip modules.
Does AEC-Q200 have temperature grades 0 to 4?: Not in the current revision. AEC-Q200 Rev E, dated 20 March 2023, sets a minimum ambient range of -40 °C to +85 °C in section 1.5.3 and asks the manufacturer to qualify each component to its own specified ambient range, using the component tables. Lists of Q200 grades 0 to 4 that circulate online describe earlier revisions. AEC-Q101 Rev E likewise has no grade table: its minimum operational range is -40 °C to +125 °C.
What ESD levels does AEC-Q100 require?: The Rev J1 targets are 2 kV HBM (classification 2 or better) and, for CDM, test condition 750 on corner pins and 500 on all other pins (classification C2A or better). For devices at 28 nm and below, or pins operating at RF frequencies, the targets are 1 kV HBM and CDM test condition 250. A level below target needs specific user approval, and an HBM target below 2 kV must be stated in the datasheet.
Does AEC-Q qualification cover functional safety?: No. AEC-Q documents qualify the physical reliability of a component under accelerated stress. Functional safety is the subject of ISO 26262, which asks for different evidence, such as failure mode analysis and diagnostic coverage. A component destined for a safety function needs both, and neither document stands in for the other.