PCB design for EMC: return paths, decoupling, stackup

Hugues Orgitello updated 7 Oct 2026 30 min read

Most of what decides a board's EMC result is fixed before the first prototype: where the return current flows, which plane each fast trace references, how much inductance sits between each IC pin and its decoupling, and how close the ESD clamp is to the connector. The reference texts for this discipline are Electromagnetic Compatibility Engineering by Henry Ott (2009) and High-Speed Digital Design by Howard Johnson and Martin Graham (1993), completed here by semiconductor application notes, each labelled as such. The product is then judged against CISPR 32 (EN 55032:2015 with A11:2020 in the EU) for emissions and against generic or product immunity standards that test ESD at 4 kV contact. This page gives the physics as formulas you can recompute, the numbers the sources actually state, and the common rules of thumb that the sources do not support.

What the board is tested against (October 2026)

The PCB does not have its own EMC standard. It is tested inside the product, at the product's ports, against the levels below. These are the values that the decisions on this page are trying to meet; the detail of each test is on the linked pages.

Phenomenon	Standard and level	Port	Where it bites on the PCB
Radiated emissions, 30 MHz to 1 GHz	CISPR 32 Class B: 30 dB(µV/m) QP from 30 to 230 MHz, 37 dB(µV/m) QP from 230 MHz to 1 GHz, at 10 m	Enclosure	Return-path loops, clock harmonics, common-mode current on cables
Conducted emissions, 150 kHz to 30 MHz	CISPR 32 Class B mains port: 66 to 56 dB(µV) QP from 0.15 to 0.5 MHz, 56 from 0.5 to 5 MHz, 60 from 5 to 30 MHz	AC mains	Switching converter input filter, ferrite bead resonances
ESD	4 kV contact, 8 kV air: EN 61000-6-1:2007, EN 61000-6-2:2005, EN 55035, EN 301 489-1 V2.2.3 clause 9.3	Enclosure	Clamp placement and return inductance at every connector
Fast transients (burst), AC mains	1 kV (EN 61000-6-1, EN 301 489-1), 2 kV (EN 61000-6-2), 5 kHz	AC mains	Input filter, ground return of the power entry
Surge, AC mains	2 kV line-to-earth, 1 kV line-to-line (EN 61000-6-1, EN 61000-6-2, EN 301 489-1)	AC mains	Creepage, clamp energy, layout of the power entry
Radiated RF immunity	3 V/m (EN 61000-6-1), 10 V/m from 80 MHz to 1 GHz (EN 61000-6-2), 3 V/m from 80 MHz to 6 GHz (EN 301 489-1)	Enclosure	Analog front ends, reset and clock lines, PLL supplies
Conducted RF immunity, 0.15 to 80 MHz	3 V (EN 61000-6-1, EN 301 489-1), 10 V (EN 61000-6-2)	Cables	Common-mode filtering where cables enter

The EU harmonised versions are EN 55032:2015 with A11:2020 for emissions, and EN 61000-6-1:2007 and EN 61000-6-2:2005 for generic immunity; the 2019 editions of the generic standards are not cited. EN 301 489-1 is used with the specific part for the radio (for example EN 301 489-17) and is not itself in the RED list. See CE tests, radiated emissions, conducted emissions, surge and burst and ESD.

The return current principle

Every signal current returns, and it returns along the path of least impedance. At low frequency the impedance of a plane is dominated by its resistance and the current spreads to take the lowest-resistance route, which is generally not under the trace. As frequency rises the inductive term dominates, and the path of least inductance is the one that encloses the smallest loop: directly beneath the signal trace in the adjacent plane. Ott develops this in section 10.6.1 (reference plane current distribution) and section 10.7 (microstrip and stripline current flow); Johnson and Graham cover it in their chapter on ground planes and layer stacking.

The frequency at which inductance takes over depends on trace geometry, plane resistance and spacing. For practical boards it sits far below 30 MHz, where the CISPR 32 radiated range starts, so for emissions work the working assumption is the high-frequency case: the return current is under the trace, and the reference plane under every fast signal must be continuous along its whole length.

Consequences of a discontinuous reference

When the reference plane is cut by a slot, a power-domain split, a cluster of anti-pads or a missing pour, the return current cannot follow under the trace. It detours around the discontinuity, and the enclosed loop grows. Ott lists the cases in section 16.3: slots in planes, split planes, changing reference planes, referencing the top and bottom of the same plane, and connectors.

Discontinuity	What the return current does	Structural fix
Slot or void under a fast trace	Detours around the end of the slot	Route around the void; TI SPRAAR7J keeps differential pairs at least 1.5 trace widths from voids
Split between two plane regions	Finds the nearest coupling between the regions	Do not route across; if unavoidable, stitching capacitors of 1 µF or lower at the crossing (TI SPRAAR7J 2.4)
Layer change between two ground planes	Needs a via between the planes near the signal via	Ground stitching vias within 5.08 mm of the signal via, closer is better (TI SPRAAR7J 2.4)
Layer change from a ground to a power reference	Needs a capacitive path between the planes	A decoupling capacitor near the transition, or avoid the change
Trace near the edge of its reference plane	Return current crowds at the plane edge	TI SPRAAR7J keeps high-speed differential pairs at least 2.29 mm (90 thousandths of an inch) from the plane edge

The old version of this table gave dB values for each discontinuity. No source supports a fixed figure: the emission depends on the loop area, the frequency, and above all on whether the loop drives common-mode current onto an attached cable.

What counts as fast

For EMC, speed is set by the edge, not by the clock frequency. Johnson and Graham define the knee frequency as f_knee = 0.5 / t_r, the frequency below which most of the energy of a digital edge lies, whatever the clock rate. The figure 0.35 / t_r, which the previous version of this page used, is a different quantity: the −3 dB bandwidth of a single-pole response with a 10 to 90 percent rise time t_r.

Rise time tr	Knee frequency 0.5 / tr (Johnson)	Single-pole bandwidth 0.35 / tr
5 ns	100 MHz	70 MHz
1 ns	500 MHz	350 MHz
500 ps	1 GHz	700 MHz
200 ps	2.5 GHz	1.75 GHz

A 10 MHz clock with 1 ns edges therefore carries harmonic energy across the whole 30 MHz to 1 GHz CISPR 32 radiated range. Slowing an edge that does not need to be fast is the cheapest emission fix there is.

Stackup choices

The stackup is fixed at fabrication. Ott section 16.4 treats one- and two-layer boards and multilayer boards; the rule that runs through both his treatment and the TI layout guide is that every high-speed signal layer should sit directly against a continuous ground plane.

4-layer: signal / GND / power / signal

Layer	Function	Reference for
1 (top)	Signal	References layer 2, ground
2	Ground plane	Return path for layer 1
3	Power plane	Plane pair with layer 2
4 (bottom)	Signal	References layer 3, power

The top layer is well served. The bottom layer references the power plane, which is fine for slow signals but is a compromise for fast ones: TI SPRAAR7J section 2.4 states that TI does not recommend referencing high-speed signals to power planes. Keep fast routing on layer 1, or move to six layers.

6 layers and more

TI SPRAAR7J section 3.12 recommends at least six layers for the high-speed SoC interfaces it covers, and gives example 6-, 8- and 10-layer arrangements in which the top signal layer sits on a ground plane, adjacent inner signal layers are routed at 90 degrees to each other, and split power planes are allowed provided traces on adjacent layers do not cross the splits. The TI 6-layer example is signal / ground / signal / signal / power or ground / signal.

Plane-pair capacitance

Two parallel planes separated by a thin dielectric form a capacitor, C = ε₀ ε_r A / d (Ott section 11.4.6, embedded PCB capacitance). With ε₀ = 8.854 pF/m and an illustrative ε_r of 4.3 (take the actual value from the laminate datasheet, at the frequency of interest):

Dielectric thickness d	Capacitance per area	10 cm × 10 cm plane pair
100 µm	38 pF/cm²	3.8 nF
200 µm	19 pF/cm²	1.9 nF
500 µm	7.6 pF/cm²	0.76 nF

The plane capacitance is small next to discrete decoupling, but it is spread over the whole board and is reached without a capacitor footprint in the way. That makes it useful at the top of the decoupling range, provided the planes are close together. It is not a reason to remove discrete capacitors.

Decoupling: the arithmetic behind the tiers

A single capacitor cannot hold a supply impedance low across the whole spectrum of a digital load. Ott chapter 11 works through multiple capacitors of the same value, of two values, of many values, and the target-impedance approach (sections 11.4.1 to 11.4.5); the conclusion is that what matters is the impedance of the network as a function of frequency, not the count of capacitors.

Every capacitor becomes an inductor

A mounted capacitor resonates at f = 1 / (2π √(L C)), where L is its own inductance plus the inductance of the mounting loop (pads, traces, vias, planes). Above that frequency it is an inductor, and its value no longer matters. The table recomputes the series resonance for two mounted inductances:

Capacitance	Resonance with 1 nH mounted	Resonance with 0.5 nH mounted
10 µF	1.59 MHz	2.25 MHz
1 µF	5.03 MHz	7.12 MHz
100 nF	15.9 MHz	22.5 MHz
10 nF	50.3 MHz	71.2 MHz
1 nF	159 MHz	225 MHz

Above resonance the impedance is close to 2πfL, whatever the capacitance:

Mounted inductance	at 100 MHz	at 300 MHz	at 1 GHz
0.5 nH	0.31 ohm	0.94 ohm	3.1 ohm
1 nH	0.63 ohm	1.9 ohm	6.3 ohm
2 nH	1.3 ohm	3.8 ohm	13 ohm

That is why mounting dominates in the range that matters for radiated emissions: halving the loop inductance halves the impedance, while changing the capacitor value does nothing once the part is past resonance.

Anti-resonance

Between two capacitors of different values there is a frequency where the smaller one is still capacitive and the larger one is already inductive. The two form a parallel resonant circuit, and the network impedance peaks. Ott sections 11.4.3 and 11.4.4 cover this case. Adding more values can create more peaks rather than removing them; the only way to know is to compute or measure the impedance of the whole network, including the planes, against a target impedance.

Mounting and via inductance

Johnson and Graham give an approximate inductance for a single via, L ≈ 5.08 h [ln(4h/d) + 1] nH, with the via length h and the barrel diameter d in inches. Recomputed for a 0.3 mm barrel:

Via length	L (approximation for an isolated via)
1.6 mm (full thickness of a common board)	1.3 nH
0.8 mm	0.54 nH

The practical consequences, all consistent with Ott section 11.7 (decoupling capacitor placement and mounting):

• Short loop: vias at or in the capacitor pads, not at the end of a fan-out trace.
• Planes close to the capacitor's side of the board: the via length that counts is the distance to the planes the current flows in.
• Parallel vias help less than their number suggests when they are close together, because of mutual inductance between them (Ott section 10.5.2). Two vias halve the inductance only if they are far enough apart to be uncoupled.
• Low-inductance packages: manufacturers offer reverse-geometry and multi-terminal capacitors designed for lower inductance; use the manufacturer's measured data for the mounted part rather than a generic percentage.

High-speed routing rules

Controlled impedance comes from the interface, not from a generic table

Above the knee frequency a trace is a transmission line, and mismatches produce reflections and ringing. The target impedance is set by the interface specification and by the layout guide of the chip vendor, and it varies between parts. The TI SPRAAR7J tables, one manufacturer's figures for its own SoC families, show the spread:

Interface	Differential impedance in TI SPRAAR7J Appendix A
USB 2.0	90 ohm (81 to 99)
USB 3.x SuperSpeed	90 ohm (83.7 to 96.3) on some families, 95 ohm (90.25 to 99.75) on others
PCI Express	100 ohm (90 to 110) on some families, 95 ohm on others
Serial ATA	100 ohm (85 to 115)
HDMI TMDS	100 ohm (90 to 110)
MIPI CSI	100 ohm (85 to 115)

RF transmission lines (Wi-Fi, BLE, sub-GHz) between radio, matching network and antenna are designed for the system impedance, normally 50 ohm; see antenna design and impedance matching. Specify impedance and tolerance in the fabrication notes and let the fabricator adjust width and spacing to its process.

Length matching and symmetry

Within a differential pair, any length difference converts part of the differential signal into common mode, and common-mode current on attached cables is a major source of product-level radiation (Ott sections 12.3 and 12.4). TI SPRAAR7J matches intra-pair lengths with serpentine added close to the mismatched end, routes pairs symmetrically, limits bends to more than 135 degrees, and notes that fibre-weave differences between the two traces of a pair create skew and AC common-mode noise. Tolerances are interface and device specific: TI gives, for example, 1.27 mm (50 thousandths of an inch) of skew within a USB 2.0 pair for one SoC family. Take the number from the device layout guide, not from a generic table.

Clock distribution

Clock lines are periodic and fast-edged, so their energy sits in discrete harmonics that line up with a narrow receiver bandwidth. Ott gives critical signals and system clocks their own sections in his layout chapter (16.1.3 and 16.1.4).

• Source termination, point to point: Johnson and Graham size the series resistor so that the driver output resistance plus the resistor equals the line impedance, R_s = Z₀ − R_driver. It removes the reflection and, because it slows the edge into the line capacitance, lowers the knee frequency.
• No stubs, no improvised daisy chains: use a fan-out buffer when several loads need the clock.
• Reference discipline: clock traces never cross a split and never change layer without a stitching via. TI SPRAAR7J keeps high-speed pairs at least 1.27 mm from clock or periodic signals.

Spread spectrum clocking (SSC)

Ott section 12.2.3 calls it the dithered clock: frequency-modulating the clock spreads each harmonic over a band, so less energy falls inside the receiver bandwidth at any one frequency. What the interface allows is fixed by its specification:

Link	SSC as stated in the source	Source
PCI Express, common reference clock	30 to 33 kHz modulation, 0 to −0.5 % spread (down-spread)	TI SNAA386, section 3.3
PCI Express, separate reference clocks with independent spread (SRIS)	Maximum down-spread −0.3 %	TI SNAA386, section 3.3
Serial ATA	+0/−5000 ppm down-spreading; the paper notes some SATA devices and hosts did not support SSC	INCITS T10 06-263r2 (2006)
Any other link	Check the receiver datasheet and the interface specification before enabling

The benefit at the test receiver depends on the width of the spread compared with the measurement bandwidth. Below 1 GHz the CISPR quasi-peak receiver uses 120 kHz. For a 0.5 % down-spread, recomputed:

Harmonic	Width of the spread	Width / 120 kHz
30 MHz	150 kHz	1.25
100 MHz	500 kHz	4.2
300 MHz	1.5 MHz	12.5
1 GHz	5 MHz	41.7

The higher harmonics gain more than the low ones, which is why SSC rarely cures a problem at the clock fundamental. TI SNAA386 shows one 100 MHz reference clock whose displayed peak moves from −5 dB to −14 dB with −0.5 % down-spread; that is one example on one instrument setting, not a general figure. Above 1 GHz CISPR 32 uses peak and average detectors with a 1 MHz bandwidth, and the gain changes again. Measure with SSC on and off.

Stitching via spacing

Ground pours and via fences are stitched to the planes so that the gaps between vias do not behave as slot antennas. A slot is resonant when its length approaches half a wavelength, so the spacing must stay well below λ/2 at the highest frequency of concern. In a stripline with ε_r = 4.3, λ = c / (f √ε_r):

Frequency	Wavelength in the dielectric	Half wavelength
1 GHz	145 mm	72 mm
3 GHz	48 mm	24 mm
6 GHz	24 mm	12 mm

The old page asked for vias every quarter wavelength. That is closer to the slot resonance than any reference here supports; space vias at a small fraction of λ/2, and closer at the edges of RF areas.

Mixed-signal and RF specifics

Crystal layout

A crystal and its load capacitors carry the reference clock of the system at high impedance, which makes them both a source and a victim. TI SPRAAR7J section 3.2 keeps high-speed traces away from crystals, oscillators, clock generators, switching regulators and magnetic devices. The other usual rules follow from the return-current principle: short connections from the crystal to the oscillator pins and load capacitors, a continuous ground under the crystal area, and no unrelated routing under it on the adjacent layer. Follow the layout section of the MCU or radio datasheet, which often specifies the arrangement.

Switching power supplies

A switching converter is an intentional source of fast di/dt. The board decisions that matter:

• Hot loop: the loop carrying the switched current (input capacitor, switches, back to the input capacitor) is kept as small as possible, with the input capacitor next to the switches and its return in the adjacent plane. Converter datasheets usually show the recommended layout; follow it.
• Switch node: sized for the current and no larger, because it is a strong near-field source; keep sensitive traces away from it and from the inductor.
• Input filter: for an AC-mains product, X capacitors line to line, Y capacitors line to protective earth, and a common-mode choke, chosen to bring the mains port under the CISPR 32 conducted limits. See common-mode filtering.
• Snubbers and shielded inductors: both can reduce ringing and near-field coupling. The size of the effect depends on the circuit; measure it rather than relying on a datasheet percentage.

Ferrite beads: the resonance trap

Analog Devices application note AN-1368 explains the failure mode from measured data:

• Manufacturers usually specify bead impedance at 100 MHz, with curves at zero DC bias.
• Below the frequency where it turns resistive, the bead behaves as an almost ideal, high-Q inductor. With the decoupling capacitor it forms a poorly damped LC filter whose resonance is typically between 0.1 and 10 MHz, in the range where many DC-DC converters switch.
• A bead filter without damping can show about 10 to 15 dB of peaking; the note measures about 10 dB at 2.5 MHz with a 100 ohm bead and a 10 nF capacitor.
• DC bias current saturates the core: at 50 % of rated current the inductance can drop by up to 90 %. The note advises using beads at about 20 % of their rated current.

Its three damping methods:

Method	Configuration	Trade-off stated in AN-1368
A	Resistor in series with the decoupling capacitor	Damps the resonance, degrades bypassing at high frequency
B	Small resistor in parallel with the bead	Damps the resonance, reduces high-frequency attenuation
C	Extra damping branch: larger capacitor in series with a resistor	Damps the resonance

The previous version of this page described the damping resistor as being in series with the capacitor in the body and in parallel with the bead in the FAQ. Both are valid, and they are different methods with different costs.

IC-level EMC data: IEC 61967 and IEC 62132

Two IEC series measure EMC at the silicon rather than at the product: IEC 61967 for emission, IEC 62132 for immunity, both maintained by subcommittee 47A of IEC technical committee 47. A board designer meets them second-hand, as numbers in a semiconductor vendor's EMC report, and the question they raise is always the same. The part is characterised as quiet on its supply pins, or as holding RF injection up to some level. What does that buy against the CISPR 32 margin measured on the finished product?

It buys a defensible comparison between candidate parts, and a ranking of the pins that deserve the decoupling and return-path discipline described earlier on this page. It does not buy dB of system margin, and the structure of the two series says so plainly.

The parts and what each one measures

Part	Method	What it measures
IEC 61967-1:2018	General conditions and definitions	Common basis, emission side
IEC 61967-2:2005	TEM cell and wideband TEM cell	Radiated emission
IEC TS 61967-3:2014	Surface scan	Near-field emission mapping
IEC 61967-4:2021	1 ohm / 150 ohm direct coupling	Conducted emission
IEC 61967-5:2003	Workbench Faraday cage	Conducted emission, withdrawn 11 October 2024
IEC 61967-6:2002	Magnetic probe	Conducted emission
IEC 61967-8:2023	IC stripline	Radiated emission
IEC 62132-1:2015	General conditions and definitions	Common basis, immunity side
IEC 62132-2:2010	TEM cell and wideband TEM cell	Radiated immunity
IEC 62132-3:2007	Bulk current injection (BCI)	Conducted immunity, withdrawn 25 December 2020
IEC 62132-4:2006	Direct RF power injection (DPI)	Conducted immunity
IEC 62132-5:2005	Workbench Faraday cage	Conducted immunity, withdrawn 6 December 2024
IEC 62132-8:2026	IC stripline	Radiated immunity
IEC TS 62132-9:2014	Surface scan	Near-field immunity mapping

Three of those parts are withdrawn, and two were revised recently: the IC stripline emission part in 2023, its immunity twin in February 2026. An undated "compliant with IEC 62132" in a datasheet settles nothing; the part number and the edition both have to appear on the report. Three parts have dropped the fixed frequency range from their titles, IEC 62132-1 in 2015, IEC 61967-1 in 2018 and IEC 61967-4 in 2021, while the two IC stripline parts took 150 kHz to 3 GHz out of their scopes in 2023 and 2026. The parts that were never revised still carry the range in their titles, IEC 62132-4:2006 among them. So "150 kHz to 1 GHz" on an IEC 61967-4 report points to the 2002 first edition, while the same string on a DPI report says nothing about the edition at all. For this page the two conducted parts matter most: IEC 61967-4 on the emission side, IEC 62132-4 on the immunity side.

The measurement is made into a defined network, on a defined board

IEC 61967-4 specifies conducted emission measurement by direct RF current measurement with a 1 ohm resistive probe, and RF voltage measurement through a 150 ohm coupling network. Its second edition, published in March 2021, reduced the recommended frequency range of the 1 ohm method to 30 MHz and added an informative Annex G on measurement in an extended frequency range above 1 GHz. IEC 62132-4 runs the experiment backwards: RF power is injected into a single pin (subclause 4.2), or into the pins of a differential-mode system (4.3), through a power injection set-up (7.2) and decoupling networks (7.5), while the IC is monitored (IEC 62132-1, subclauses 6.6.5 and 7.4.5) and the outcome is expressed against the IC performance classes of IEC 62132-1 subclause 8.3.

Three things are fixed by the method, and not one of them is your design.

• The board. Both general parts carry a general test board description, informative in each case: Annex D of IEC 61967-1, Annex B of IEC 62132-1. In IEC 62132-1 that annex runs down to ground planes, package pins, via diameters, via spacing, supply decoupling and I/O loading. It is a reference board built for reproducibility between laboratories, not a model of your stackup.
• The network at the pin. One ohm to develop a measurable RF current, 150 ohm to develop a measurable RF voltage. The 150 ohm value is not arbitrary: IEC 61967-4 identifies its impedance matching network as the one corresponding with IEC 61000-4-6, and IEC 62132-4 cites IEC 61000-4-6 normatively as well.
• The instrument. The single normative reference of IEC 61967-1 is CISPR 16-1-1, the measuring-apparatus standard. IEC 62132-4 additionally cites CISPR 16-1-2, the same ancillary-equipment standard that defines the LISN used for conducted emissions at product level.

That shared instrumentation lineage is what makes the two families of numbers look comparable. They are not. A CISPR 32 conducted result is a disturbance voltage at the product's power port, developed across the LISN reference impedance, with your board, your enclosure and your cable set in the loop. An IEC 61967-4 result is a current or a voltage at one pin of one IC on a reference board. Same units, different port, different network, different boundary. There is no published transfer function from one to the other, and there cannot be a general one: the missing terms are your stackup, your decoupling, your cable lengths and your enclosure, which is to say the rest of this page.

Correlation, not conversion

Neither general part promises a conversion. Both give the question its own subclause and call it correlation: IEC 61967-1 subclause 8.8.3 and IEC 62132-1 subclause 8.4.3 are both titled "Correlation to module test methods". Each sits beside a subclause on comparison between ICs using the same test method, and another on comparison between different test methods. The shape of clause 8 is the committees' own answer about what is safe: same method, same conditions, one candidate against another. Anything beyond that is an argument you have to build yourself, and defend at the design review.

IEC 61967-4 states the dependency in the opposite direction, in its opening clause on measurement basics. The emission level an IC may be allowed follows from the emission level permitted to the electronic system that contains it, and from the immunity of the other parts of that system, and it moves with system-specific and application-specific ambient parameters. The standard derives an IC budget from a system requirement. It offers no inverse.

Where the numbers in a vendor report come from

A report that quotes a class or a level is quoting an informative annex. In IEC 61967-4 the classification of conducted emission levels is Annex B, informative, and the reference levels for automotive applications are Annex C, informative. In IEC 62132-4 the example immunity level ranges are Annex A, informative. In both general parts the limits subclause sits inside clause 8, the test report: IEC 61967-1 subclause 8.7, "RF emission limits", and IEC 62132-1 subclause 8.2, "Immunity limits or levels". What these series standardise is how a number is produced and reported, not what the number has to be. Where an IC-level limit binds, it binds because a purchasing specification made it bind.

What the IC was executing while it was measured can move the result as much as the board does, which is why IEC 61967-1 gives subclause 6.5.3 to the activity of the IC and subclause 6.5.4 to guidelines regarding IC operation, and adds two informative annexes, one on a counter test code and one on worst-case application software. A report that does not state the operating mode is not comparable to anything, including the next report from the same vendor.

The regulatory gate

Neither series is harmonised. No part of IEC 61967 or IEC 62132 appears in Commission Implementing Decision (EU) 2019/1326, the list of harmonised standards drafted in support of the EMC Directive, whose consolidated text has not moved since 10 June 2022. EN 55032:2015, the European version of CISPR 32, is item 13 on that list. An IC-level EMC report is supplier design data: it can sit in the design file as component evidence, but it earns no presumption of conformity and it does not stand in for a product test. See EMC harmonised standards, no citation since 2022 for the state of the list, and harmonised standards and presumption of conformity for what citation actually buys.

Reading a vendor report

Question	What an IC-level report can settle
Which of two candidate parts is quieter on this rail?	Yes, if both were measured by the same part of the series, in the same edition, running comparable software
Which pins deserve the tightest decoupling and the shortest return path?	Yes, as a ranking, which is design input for the rules earlier on this page
Will the product clear the CISPR 32 class B limit, and by how much?	No
Can the report stand in for a product-level emission test?	No
Is a DPI immunity level a substitute for IEC 61000-4-6 on the product?	No. Different port, different injection network, different EUT boundary
Is a TEM cell figure comparable to a 1 ohm figure on the same IC?	Not directly. Both general parts give cross-method comparison its own subclause precisely because it is not straightforward

The practical posture is the one this page takes. Take the quieter part when the choice is free, then design as though the report did not exist: uninterrupted return path under every fast signal, ground adjacent to fast routing, decoupling mounted for minimum loop inductance. The margin is decided by the board, the enclosure and the cables, and it is measured at the product's ports, not at the IC pins. For those measurements see conducted emissions, radiated emissions and IEC 61000-4-6 conducted RF immunity.

Cables, shielding, ESD entry

Cable shielding and pigtails

External cables carry conducted emissions out of the product and conducted disturbances in, and above 30 MHz they are often the antenna. A shield works at high frequency only if it is bonded 360 degrees to the connector shell and the shell to the chassis or the board reference. Ott section 2.15.1 treats the pigtail, a shield gathered into a single wire, as the classic failure: the wire's inductance sits in series between the shield and the reference. Its reactance is 2πfL:

Pigtail inductance	at 30 MHz	at 100 MHz	at 300 MHz
10 nH	1.9 ohm	6.3 ohm	19 ohm
20 nH	3.8 ohm	13 ohm	38 ohm
50 nH	9.4 ohm	31 ohm	94 ohm

Any shield current flowing through that reactance develops a common-mode voltage that drives the outside of the cable. On the board, the connector shell needs a low-inductance, multi-via connection to the reference the design uses for I/O (Ott section 16.2 covers the PCB-to-chassis ground connection).

Common-mode chokes on cable entries

A common-mode choke presents high impedance to current flowing in the same direction on all its windings and little to the differential signal. It belongs at the cable entry, between the connector and the rest of the board, so that it acts on the common-mode current before it reaches the cable. Ott section 12.4.2 covers cable filtering and shielding. TI SPRAAR7J section 3.14 groups the AC coupling capacitors, the common-mode filter and the ESD protection as close as possible to the connector, with any vias to the filter layer placed next to the filter.

ESD entry points

Every external port is a potential ESD entry: USB, Ethernet, audio, power input, buttons, exposed metal and antenna connectors. The levels that the protection has to handle, as stated by the standards in force:

Standard	Contact discharge	Air discharge
EN 61000-6-1:2007 (residential, commercial, light industrial)	4 kV	8 kV
EN 61000-6-2:2005 (industrial)	4 kV	8 kV
EN 55035 (multimedia immunity)	4 kV	8 kV
EN 301 489-1 V2.2.3, clause 9.3 (radio equipment)	±4 kV	±8 kV

Higher levels apply where a product standard asks for them; the ESD guide lists the IEC 61000-4-2 ladder and the medical case. The test method itself is IEC 61000-4-2 (IEC basic publication), now in Edition 3.0 of 7 March 2025; when a product standard dates its reference to the 2008 edition, that edition governs the test.

In the 2008 edition (Table 2), the contact-discharge current has a first peak of 3.75 A per kV, so 15 A at 4 kV and 30 A at 8 kV, with a rise time of 0.8 ns plus or minus 25 percent. A crude estimate of the voltage that inductance in the clamp path adds is V = L × di/dt:

Inductance in the clamp path	Added voltage at 4 kV contact (15 A in 0.8 ns)
1 nH	about 19 V
5 nH	about 94 V

That is on top of the clamp voltage of the protection device, and it is why placement and return matter more than the device rating:

1. Protection at the connector: TI SPRAAR7J section 3.14 places ESD and EMI protection devices as close as possible to the connector and keeps unprotected traces away from protected ones. Ott section 15.5 addresses preventing ESD entry at enclosures, cables and keyboards.
2. Short return: the protection device returns directly to the reference at the connector (chassis or I/O ground), through vias next to its pad, not along a trace to a distant ground point.
3. Impedance between clamp and IC: a series element, chosen within the signal integrity budget of the line, makes the clamp the lower-impedance path for the pulse.
4. Flow-through routing: TI SPRAAR7J section 3.13 prefers protection devices whose pinout lets the differential pair pass straight through without bends.

The method and the waveform are detailed in ESD IEC 61000-4-2; radiated field coupling into the board is covered by radiated immunity.

Pitfalls that fail formal test

The recurring causes, each tied to the mechanism the references describe. None has a fixed dB penalty: the effect depends on frequency, loop and cabling, and is only known once the product is measured.

Pitfall	Mechanism	Reference
Fast signal across a plane split or void	Return current detours, loop area grows	Ott 16.3.1 and 16.3.2; TI SPRAAR7J 2.4
Layer change with no stitching via or capacitor nearby	Return current changes plane far from the signal via	Ott 16.3.3; TI SPRAAR7J 2.4
High-speed signals referenced to a power plane	Return path depends on decoupling between planes	TI SPRAAR7J 2.4
Decoupling reached through long traces or vias	Mounted inductance sets the impedance above resonance	Ott 11.7; arithmetic above
Clock without termination, with stubs or daisy chain	Reflections, ringing, extra harmonic content	Johnson and Graham, terminations and clock distribution
ESD protection away from the connector, or with a long return	Inductance adds voltage, pulse reaches the IC	TI SPRAAR7J 3.14; Ott 15.5
Common-mode filter away from the cable entry	Common-mode current reaches the cable first	Ott 12.4.2; TI SPRAAR7J 3.14
Pigtail shield termination	Shield current develops a voltage across the pigtail	Ott 2.15.1
Ferrite bead on a sensitive rail without damping	Poorly damped LC resonance, often at converter frequencies	ADI AN-1368
Ferrite bead run near its rated current	Inductance collapses with DC bias	ADI AN-1368
SSC enabled on a link that does not allow it	Link loss or data errors	TI SNAA386; T10 06-263r2

Claims the texts contradict

Rules of thumb travel from page to page without their source. These are the ones this page carried before its October 2026 revision, or that circulate widely, set against what the texts say.

Common claim	What the source says
"The knee frequency is fknee = 0.35 / tr"	Johnson and Graham define fknee = 0.5 / tr. 0.35 / tr is the −3 dB bandwidth of a single-pole response, a different quantity
"USB 3.x, PCIe and HDMI are all 100 ohm differential"	TI SPRAAR7J lists 90 ohm for USB 3.x SuperSpeed on some SoC families and 95 ohm on others, 100 or 95 ohm for PCIe depending on the family, 100 ohm for HDMI. The target comes from the device layout guide
"PCIe allows SSC via SRIS"	Common-clock PCIe specifies 30 to 33 kHz with 0 to −0.5 % spread; SRIS is the separate-clock case, limited to −0.3 % (TI SNAA386)
"SSC lowers the quasi-peak reading by 6 to 10 dB"	No reference states a fixed gain. It depends on the spread width against the 120 kHz CISPR bandwidth, so on the harmonic number; TI shows a single example of one clock
"Size the TVS for the typical 8 kV contact discharge"	EN 61000-6-1:2007, EN 61000-6-2:2005, EN 55035 and EN 301 489-1 V2.2.3 test at 4 kV contact and 8 kV air. 8 kV contact is a higher level that only some product standards require
"IEC 61000-4-2 (2008) is the current ESD method"	Edition 3.0 was published on 7 March 2025 and replaces the 2008 edition; product standards dated to 2008 still govern which edition applies to a given test
"Damp a ferrite bead with 0.5 to 2 ohm in parallel" and "the bead resonance is in the hundreds of MHz"	AN-1368 gives three damping methods (series resistor with the capacitor, parallel resistor across the bead, RC damping branch) and puts typical bead and capacitor resonances between 0.1 and 10 MHz
"Two vias halve the inductance, four quarter it"	True only for vias far enough apart to be uncoupled; mutual inductance reduces the gain when they are close (Ott 10.5.2)
"Stitch ground pours every quarter wavelength"	A gap resonates as a slot as its length approaches half a wavelength; quarter-wave spacing is too close to that. Keep spacing at a small fraction of λ/2
"Each pitfall adds about 10 dB" and the other fixed dB figures for slots, splits, shielded inductors and series resistors	No source on this page gives such figures. They have been removed
"CISPR 32:2015+A1:2019 is the EU emission reference"	The EU cites EN 55032:2015 with A11:2020; CISPR 32 Amendment 1 is not part of the cited reference

Going further

• Radiated emissions test: how the design choices on this page are measured under CISPR 32
• IEC 61000-4-3 radiated RF immunity: the mirror test, where the board must survive incoming RF
• IEC 61000-4-6 conducted RF immunity: cable common-mode injection and its PCB consequences
• ESD IEC 61000-4-2: waveform and test method that drive ESD entry-point design
• Surge and burst IEC 61000-4-5 and 4-4: the power-entry levels in the table at the top of this page
• Pre-compliance with TEM cell and near-field probes: debugging tools that find these pitfalls before the formal lab
• Glossary: EMC terms used on this page

See also

• What is EMC? Emissions, immunity and coupling
• Where return current actually flows - the physics behind the return-path rules above
• Decoupling, ESL and anti-resonance - why three tiers, and where the tiers fight each other
• Common-mode filtering - the theory behind the converter input filter
• How energy couples: radiation, conduction, crosstalk
• Rise time and the spectral envelope - what an edge rate costs you in bandwidth
• Antenna design and impedance matching for IoT
• Radio: RX blocking, selectivity and intermodulation tests
• Radiated emissions EMC test: pre-scan and final scan
• Pre-compliance EMC: TEM cell, near-field probes, LISN

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Sources & references

1. Henry W. Ott, Electromagnetic Compatibility Engineering (2009), Wiley, Wiley onlinelibrary.wiley.com/doi/book/10.1002/9780470508510
2. Henry W. Ott, Electromagnetic Compatibility Engineering, detailed table of contents (section numbers cited on this page), Henry Ott Consultants hott.shielddigitaldesign.com/EMCE_book_files/detail_contents.html
3. Signal Consulting, Howard W. Johnson and Martin Graham, High-Speed Digital Design (1993), Prentice Hall, Prentice Hall www.sigcon.com/
4. Howard Johnson, Erroneous Harmonics, High-Speed Digital Design newsletter vol. 4 issue 9 (knee frequency 0.5/tr), Signal Consulting www.sigcon.com/Pubs/news/4_9.htm
5. Texas Instruments SPRAAR7J, High-Speed Interface Layout Guidelines (revised February 2023), manufacturer application note, Texas Instruments www.ti.com/lit/an/spraar7j/spraar7j.pdf
6. Texas Instruments SNAA386, Clocking for PCIe Applications (November 2023), manufacturer application note, Texas Instruments www.ti.com/lit/an/snaa386/snaa386.pdf
7. INCITS T10 06-263r2, SAS-2 spread-spectrum clocking (22 June 2006), committee proposal, INCITS T10 www.t10.org/ftp/t10/document.06/06-263r2.pdf
8. Analog Devices AN-1368, Ferrite Bead Demystified (Jefferson Eco and Aldrick Limjoco), manufacturer application note, Analog Devices www.analog.com/en/resources/app-notes/an-1368.html
9. CISPR 32:2015+A1:2019, Electromagnetic compatibility of multimedia equipment, emission requirements, IEC webstore.iec.ch/publication/22046
10. IEC 61000-4-2:2025 (Edition 3.0), electrostatic discharge immunity test, IEC webstore.iec.ch/en/publication/68954
11. ETSI EN 301 489-1 V2.2.3 (2019-11), EMC standard for radio equipment, common technical requirements, ETSI www.etsi.org/deliver/etsi_en/301400_301499/30148901/02.02.03_60/en_30148901v020203p.pdf
12. IEC 61967-1:2018, Integrated circuits, measurement of electromagnetic emissions, part 1: general conditions and definitions, IEC webstore.iec.ch/en/publication/59799
13. IEC 61967-4:2021, Measurement of conducted emissions, 1 ohm/150 ohm direct coupling method, IEC webstore.iec.ch/en/publication/64113
14. IEC 62132-1:2015, Integrated circuits, measurement of electromagnetic immunity, part 1: general conditions and definitions, IEC webstore.iec.ch/en/publication/23626
15. IEC 62132-4:2006, Measurement of electromagnetic immunity, part 4: direct RF power injection method, IEC webstore.iec.ch/en/publication/6510
16. Commission Implementing Decision (EU) 2019/1326 on the harmonised standards for electromagnetic compatibility, consolidated text of 10 June 2022, EUR-Lex eur-lex.europa.eu/legal-content/EN/TXT/?uri=CELEX:02019D1326-20220610