Why does a capacitor stop working above a certain frequency?

Because it is a capacitor in series with an inductance, its equivalent series inductance, contributed by the part itself and by how it is mounted. The two resonate at one over two pi root LC. Below that the impedance falls with frequency, as a capacitor should. Above it the inductance dominates and the impedance rises, so the part behaves as an inductor. A 100 nF capacitor with 1 nH of total inductance is resonant near 15.9 MHz, which means it does nothing useful for a 100 MHz problem no matter how many are fitted.

Why can two capacitor values be worse than one?

Because between the two self-resonances one part has gone inductive while the other is still capacitive, and an inductance in parallel with a capacitance is a parallel resonator that peaks. A 1 uF part at 1.5 nH resonates near 4.1 MHz and a 100 nF part at 0.8 nH near 17.8 MHz. Between them, at about 11 MHz, the pair presents roughly 800 mΩ while either capacitor on its own presents about 90. The combination is around nine times worse than one part at that frequency, which is the opposite of what adding a component is supposed to do.

What should be done instead of mixing values?

Use many capacitors of the same value, placed well. Ten identical 100 nF parts in parallel divide the impedance by ten at every frequency, leave the self-resonance where it was, and introduce no new peak, because there is no second resonance to beat against. Where a genuinely different frequency range must be covered, keep the values far enough apart that the anti-resonance falls outside the band that matters, and rely on ESR to damp what remains. A capacitor with slightly higher ESR is sometimes the better part.

How much decoupling is enough?

Set a target impedance from the rail rather than guessing a count. Z target equals the permitted ripple voltage divided by the largest expected current step. A 1.0 V rail allowed 3 percent ripple under a 5 A step needs 6 mΩ; a 3.3 V rail at 5 percent under 2 A needs 82.5 mΩ. The decoupling network then has to stay under that figure across the frequency range where the load actually steps. Stated that way the question becomes measurable, and it usually shows that the constraint is inductance rather than capacitance.

Decoupling: ESL, self-resonance, anti-resonance

Author Hugues Orgitello Last updated 29 August 2026 ~4 min read

Guide, EMC fundamentals

A decoupling capacitor is a capacitor only below its resonant frequency. Above it, the part is an inductor, and adding more of the wrong kind can make the impedance worse rather than better. This page derives where that boundary sits, shows that layout moves it further than component choice does, and quantifies the case where two capacitors are nine times worse than one.

Every capacitor is an LC circuit

A real capacitor is capacitance in series with resistance and inductance. The inductance, its ESL, comes partly from the part and mostly from the loop the mounting creates: pads, traces, vias, and the path through the planes.

Capacitance and inductance resonate at:

f0 = 1 / (2 pi sqrt(L C))

Below f0 the impedance falls with frequency. Above it the impedance rises. The part stops decoupling and starts obstructing.

Value	ESL 0.5 nH	1 nH	2 nH	5 nH
1 uF	7.1 MHz	5.0 MHz	3.6 MHz	2.3 MHz
100 nF	22.5 MHz	15.9 MHz	11.3 MHz	7.1 MHz
10 nF	71.2 MHz	50.3 MHz	35.6 MHz	22.5 MHz
1 nF	225 MHz	159 MHz	113 MHz	71.2 MHz
100 pF	712 MHz	503 MHz	356 MHz	225 MHz

Read across a row rather than down a column: the same part moves by a factor of three depending on inductance alone.

Mounting beats the part number

Take one 100 nF capacitor and change nothing but how it is fitted:

Mounting	Loop inductance	Self-resonance
Ideal 0402, no via	0.6 nH	20.5 MHz
Short via pair	1.2 nH	14.5 MHz
Longer trace plus via	2.5 nH	10.1 MHz
Via stub, or via placed far away	5.0 nH	7.1 MHz

A factor of three in useful bandwidth, decided entirely by layout, on an identical component. PCB design for EMC notes the same effect from the layout side: the same 1 nF part can show anywhere between 0.3 and 3 nH depending on mounting.

The practical order of priority follows from this. Shorten the loop from pad to plane first, choose the package second, and worry about the dielectric last. A reverse-geometry part on a long via stub is a worse decoupling capacitor than an ordinary part mounted tightly.

What the impedance actually does

A 100 nF part with 1 nH and 10 mΩ of resistance:

Frequency	Impedance	Behaviour
100 kHz	15915 mΩ	capacitive
1 MHz	1585 mΩ	capacitive
5 MHz	287 mΩ	capacitive
15.9 MHz	10 mΩ	at resonance, ESR only
50 MHz	283 mΩ	inductive
200 MHz	1249 mΩ	inductive

At resonance the impedance is just the resistance, which is the best the part will ever do. Either side of it, impedance rises.

Two values can be worse than one

This is the result that surprises people, so it is worth stating in numbers.

Take a 1 uF part with 1.5 nH ESL and a 100 nF part with 0.8 nH, both low-ESR ceramics. Their self-resonances are 4.1 MHz and 17.8 MHz. Between those frequencies the 1 uF part has gone inductive while the 100 nF part is still capacitive, and an inductance in parallel with a capacitance is a parallel resonator.

Sweeping the pair between its two resonances finds the peak:

At 11.0 MHz	Impedance
1 uF alone	89.3 mΩ
100 nF alone	89.6 mΩ
Both in parallel	800 mΩ

The pair is roughly nine times worse than either capacitor on its own, at a frequency squarely inside the range a digital design cares about. Adding a component made the rail worse.

What to do instead

Use many identical parts. Ten 100 nF capacitors in parallel divide the impedance by ten at every frequency, leave the self-resonance exactly where it was, and create no new peak, because there is no second resonance to beat against:

Count of 100 nF	Impedance at 20 MHz
1	21.5 mΩ
4	5.4 mΩ
10	2.2 mΩ

Where two ranges genuinely must be covered, separate the values far enough that the anti-resonance lands outside the band that matters, and accept some ESR. A part with slightly higher resistance damps the peak; the lowest-ESR capacitor available is not always the right choice.

Plot Z against f for the network before committing. The anti-resonance is invisible in a schematic and obvious in a plot.

How much is enough

Rather than counting capacitors, set a target impedance from the rail itself:

Z target = permitted ripple voltage / largest current step

Rail	Ripple	Step	Z target
1.0 V	3 %	5 A	6.0 mΩ
3.3 V	5 %	2 A	82.5 mΩ
1.8 V	5 %	10 A	9.0 mΩ

The network must stay below that figure across the frequency range where the load actually steps. Framed this way the question becomes measurable, and it usually reveals that the binding constraint is inductance, not capacitance: adding another microfarad does nothing if the loop inductance already sets the floor.

Key takeaways

Every capacitor is an inductor above its self-resonance, at f0 = 1/(2 pi sqrt(LC)).
Mounting moves that frequency by a factor of three on an identical part. Shorten the loop before choosing the package.
At resonance the impedance is just ESR, which is the best the part will ever achieve.
Two values can be nine times worse than one. A 1 uF and a 100 nF pair peaks at 800 mΩ around 11 MHz where either alone gives 90.
Many identical parts scale cleanly and add no new peak.
Set a target impedance from ripple over current step, then check the constraint is not inductance.

Frequently asked questions

Why does a capacitor stop working above a certain frequency?: Because it is a capacitor in series with an inductance, its equivalent series inductance, contributed by the part itself and by how it is mounted. The two resonate at one over two pi root LC. Below that the impedance falls with frequency, as a capacitor should. Above it the inductance dominates and the impedance rises, so the part behaves as an inductor. A 100 nF capacitor with 1 nH of total inductance is resonant near 15.9 MHz, which means it does nothing useful for a 100 MHz problem no matter how many are fitted.
Does the mounting really matter more than the part?: Usually, yes. The same 100 nF capacitor resonates at 20.5 MHz with 0.6 nH of loop inductance, at 14.5 MHz with a short via pair, at 10.1 MHz with a longer trace and via, and at 7.1 MHz on a via stub. That is a factor of three in useful bandwidth decided entirely by layout, on an identical component. Choosing a lower-ESL package buys less than shortening the loop from pad to plane, which is why capacitor placement and via strategy are worth more attention than the part number.
Why can two capacitor values be worse than one?: Because between the two self-resonances one part has gone inductive while the other is still capacitive, and an inductance in parallel with a capacitance is a parallel resonator that peaks. A 1 uF part at 1.5 nH resonates near 4.1 MHz and a 100 nF part at 0.8 nH near 17.8 MHz. Between them, at about 11 MHz, the pair presents roughly 800 mΩ while either capacitor on its own presents about 90. The combination is around nine times worse than one part at that frequency, which is the opposite of what adding a component is supposed to do.
What should be done instead of mixing values?: Use many capacitors of the same value, placed well. Ten identical 100 nF parts in parallel divide the impedance by ten at every frequency, leave the self-resonance where it was, and introduce no new peak, because there is no second resonance to beat against. Where a genuinely different frequency range must be covered, keep the values far enough apart that the anti-resonance falls outside the band that matters, and rely on ESR to damp what remains. A capacitor with slightly higher ESR is sometimes the better part.
How much decoupling is enough?: Set a target impedance from the rail rather than guessing a count. Z target equals the permitted ripple voltage divided by the largest expected current step. A 1.0 V rail allowed 3 percent ripple under a 5 A step needs 6 mΩ; a 3.3 V rail at 5 percent under 2 A needs 82.5 mΩ. The decoupling network then has to stay under that figure across the frequency range where the load actually steps. Stated that way the question becomes measurable, and it usually shows that the constraint is inductance rather than capacitance.